Designing and Mapping of a Turbo Decoder for 3G Mobile Systems Using Dynamically Reconfigurable Architecture

Turbo codes enable high quality communication links by offering exceptional error correction capabilities. Turbo coding is proposed in the coming Universal Mobile Telecommunication Systems (UMTS) standard by the 3GPP for high data rates channels. Direct realization of the Turbo decoder algorithm in hardware encounters many challenges, such as algorithm complexity, large silicon area, high power consumption and low throughput. Reconfigurable computing is emerging as a favorable solution that provides flexibility and power savings without noticeable sacrifice in performance. As a possible application, a Turbo decoder compatible with 3GPP standard is designed and mapped onto new dynamically reconfigurable architecture that is specifically designed for the 3 generation and future wireless mobile terminals. The implementation exploits the parallelism in the Turbo decoder algorithm and shows the possibilities of the architecture to be dynamically reconfigured in time and space. Simulation results are given.